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1 of 20 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds1553 is a full-function, year-2000- compliant (y2kc) real-time clock/calendar (rtc) with an rtc alarm, watchdog timer, power-on reset, battery monitor, and 8k x 8 nonvolatile static ram. user access to all registers within the ds1553 is accomplished with a byte-wide interface as shown in figure 1. the rtc registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour bcd format. corrections for day of month and leap year are made automatically. pin configurations appear at end of data sheet. features ? integrated nv sram, rtc, crystal, power-fail control circuit, and lithium energy source ? clock registers are accessed identically to the static ram; these registers are resident in the 16 top ram locations ? totally nonvolatile with over 10 years of operation in the absence of power ? precision power-on reset ? programmable watchdog timer and rtc alarm ? bcd-coded year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 ? battery voltage level indicator flag ? power-fail write protection allows for ? 10% v cc power-supply tolerance ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ordering information part voltage (v) temp range pin-package top mark** ds1553-85+ 5.0 0c to +70c 28 edip (0.740) ds1553+85 ds1553-100+ 5.0 0c to +70c 28 edip (0.740) ds1553+100 ds1553w-120+ 3.3 0c to +70c 28 edip (0.740) ds1553w+120 ds1553w-150+ 3.3 0c to +70c 28 edip (0.740) ds1553w+150 DS1553P-85+ 5.0 0c to +70c 34 powercap* ds1553p+85 ds1553p-100+ 5.0 0c to +70c 34 powercap* ds1553p+100 ds1553wp-120+ 3.3 0c to +70c 34 powercap* ds1553wp+120 ds1553wp-150+ 3.3 0c to +70c 34 powercap* ds1553wp+150 ds9034pcx+ 3 0c to +70c ds9034pcx + denotes a lead(pb)-free/rohs-compliant package. * powercap required, must be ordered separately ** a + symbol anywhere on the top mark indicates a lead(pb)-free package. ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram www.maxim-ic.com 19-5480 ; rev 8/10 downloaded from: http:///
ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 2 of 20 pin description pin edip powercap name function 1 2 rst active-low power-on reset output (open drain) 2 30 a12 3 25 a7 4 24 a6 5 23 a5 6 22 a4 7 21 a3 8 20 a2 9 19 a1 10 18 a0 21 28 a10 23 29 a11 24 27 a9 25 26 a8 address inputs 11 16 dq0 12 15 dq1 13 14 dq2 15 13 dq3 16 12 dq4 17 11 dq5 18 10 dq6 19 9 dq7 data input/outputs 20 8 ce active-low chip enable 22 7 oe active-low output enable 26 1 irq /ft active-low interrupt/frequency test output (open drain) 27 6 we active-low write enable 28 5 v cc power-supply input 17 gnd ground 2, 3, 31C34 n.c no connection downloaded from: http:///
ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 3 of 20 detailed description the rtc registers in the ds1553 are doubl e-buffered into an internal and ex ternal set. the user has direct access to the external set. clock/calendar updates to th e external set of registers can be disabled and enabled to allow the user to access st atic data. assuming the internal osc illator is turned on, the internal set of registers is contin uously updated. this occurs regardless of ex ternal registers settings to guarantee that accurate rtc information is always maintained. the ds1553 has interrupt ( irq /ft) and reset ( rst ) outputs that can be used to control cpu activity. the irq /ft interrupt output can be used to generate an external inte rrupt when the rtc register values match user-programmed alarm values. the interrupt is always available while the device is powered from the system supply, and it can be programmed to occur when in the battery-backed state to serve as a system wakeup. either the irq /ft or rst outputs can also be used as a cpu watchdog timer. cpu activity is monitored and an interrupt or reset output is activ ated if the correct activity is not detected within programmed limits. the ds1 553 power-on reset can be used to detect a system power-down or failure and can hold the cpu in a safe reset stat e until normal power retu rns and stabilizes. the rst output is used for this function. the ds1553 also contains its own power-fail circuitry, which automatically deselects the device when the v cc supply enters an out-of-toleran ce condition. this feature provides a high degree of data security during unpredictable system operation brought on by low v cc levels. packages the ds1553 is available in a 28-pin dip and a 34-pin powercap module. the 28-pin dip module integrates the crystal, lithium en ergy source, and silicon in one p ackage. the 34-pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the powe rcap to be mounted on top of the ds1553p after completion of the surface-mount process. mounti ng the powercap after the surface-mount process prevents damage to the crystal and battery due to the high temperatures require d for solder reflow. the powercap is keyed to prevent re verse insertion. the powercap modul e board and powercap are ordered separately and shipped in sepa rate containers. the part numbe r for the powercap is ds9034pcx. figure 1. block diagram downloaded from: http:///
ds1553 64kb, nonvolatile, year-2000-compliant timekeeping ram 4 of 20 table 1. operating modes v cc ce oe we dq0Cdq7 mode power v ih x x high-z deselect standby v il x v il d in write active v il v il v ih d out read active v cc > v pf v il v ih v ih high-z read active v so < v cc ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 5 of 20 below v so . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. all control, data, and address signa ls must be powered down when v cc is powered down. battery longevity the ds1553 has a lithium power sour ce that is designed to provide energy for the clock activity and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the ds1553 continuously for the life of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at +25 ? c with the internal clock oscillator running in the absence of v cc . each ds1553 is shipped from dallas semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is en abled for battery backup operation. internal battery monitor the ds1553 constantly monitors the battery voltage of the internal battery. the battery low flag (blf) bit of the flags register (b4 of 1ff0 h) is not writeable and should always be 0 when read. if a 1 is ever present, an exhausted lithium energy source is indi cated, and both the contents of the rtc and ram are questionable. power-on reset a temperature-compensated comparator circuit monitors the v cc level. when v cc falls to the power-fail trip point, the rst signal (open drain) is pulled low. when v cc returns to nominal levels, the rst signal continues to be pulled low for 40ms to 200ms. the power-on reset function is independent of the rtc oscillator and is therefore operational wh ether or not the osci llator is enabled. downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 6 of 20 clock operations table 2 and the following paragraphs describe th e operation of rtc, alar m, and watchdog functions. table 2. register map data address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function/range 1fffh 10 year year year 00-99 1ffeh x x x 10 m month month 01-12 1ffdh x x 10 date date date 01-31 1ffch x ft x x x day day 01-07 1ffbh x x 10 hour hour hour 00-23 1ffah x 10 minutes minutes minutes 00-59 1ff9h osc 10 seconds seconds seconds 00-59 1ff8h w r 10 century century control 00-39 1ff7h wds bmb 4 bmb3 bmb2 bmb 1 bmb 0 rb 1 rb0 watchdog 1ff6h ae y abe y y y y y interrupts 1ff5h am4 y 10 date date alarm date 01-31 1ff4h am3 y 10 hours hours alarm hours 00-23 1ff3h am2 10 minutes minutes alarm minutes 00-59 1ff2h am1 10 seconds seconds alarm seconds 00-59 1ff1h y y y y y y y y unused 1ff0h wf af 0 blf 0 0 0 0 flags x = unused, read/writable under write and read bit control ae = alarm flag enable ft = frequency test bit y = unused, read/wri table without write and read bit control osc = oscillator start/stop bit abe = alarm in battery-backup mode enable w = write bit am1Cam4 = alarm mask bits r = read bit wf = watchdog flag wds = watchdog steering bit af = alarm flag bmb0Cbmb4 = watchdog multiplier bits 0 = 0 read only rb0Crb1 = watchdog resolution bits blf = battery low flag clock oscillator control the clock oscillator may be stopped at any time. to increase the shel f life of the backup lithium battery source, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb of the seconds register (b7 of 1ff9h). setting it to 1 stops the oscillator; se tting it to 0 starts the oscillator. the ds1553 is shipped fr om dallas semiconductor with the clock oscillator turned off, with the osc bit set to 1. downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 7 of 20 reading the clock when reading the rtc data, it is recommended to halt updates to the external set of double-buffered rtc registers. this puts the external registers into a static state, allowing data to be read without register values changing during the read process. normal updates to the internal registers continue while in this state. external updates are ha lted when a 1 is written in to the read bit, b6 of the control register (1ff8h). as long as a 1 remains in the control register read bit, updating is halted. after a halt is issued, the registers reflect the rtc count (day, date, and time) that was current at the moment the halt command was issued. normal updates to the extern al set of registers resu me within 1 second afte r the read bit is set to 0 for a minimum of 500 ? s. the read bit must be 0 for a minimum of 500 ? s to ensure the external registers are updated. setting the clock the 8th bit, b7 of the control regist er, is the write bit. setting the write bit to 1, like the read bit, halts updates to the ds1553 (1ff8hC1fffh) registers. after se tting the write bit to 1, rtc registers can be loaded with the desired rtc count (day, date, and time) in 24-hour bcd format. setting the write bit to 0 then transfers the values written to the internal rtc registers and allows normal operation to resume. clock accuracy (dip module) the ds1553 is guaranteed to k eep time accuracy to within ? 1 minute per month at +25 ? c. the rtc is calibrated at the factory by dallas semiconductor usi ng nonvolatile tuning elements and does not require additional calibration. for this reason, methods of field clock calibration are not available and not necessary. the electrical environmen t also affects clock accuracy and caution should be ta ken to place the rtc in the lowest level emi section of the pc board layout. for additional information, refer to application note 58: crystal consider ations with dallas real-time clocks , available on our website at www.maxim-ic.com/appnoteindex.com . clock accuracy (p owercap module) the ds1553 and ds9034pcx are each individually tested for accuracy. once mounted together, the module typically keeps time accuracy to within ? 1.53 minutes per month (35ppm) at +25c. the electrical environment affects cloc k accuracy and caution should be taken to place the rtc in the lowest level emi section of the pc board layout. for additional information, refer to application note 58: crystal considerations with dallas real-time clocks , available on our website at www.maxim-ic.com/appnoteindex.com . frequency test mode the ds1553 frequency test mode uses the open-drain irq /ft output. with the oscillator running, the irq /ft output toggles at 512hz when the ft bit is 1, the alarm flag enable bit (ae) is 0, and the watchdog steering bit (wds) is 1 or the watchdog re gister is reset (register 1ff7h = 00h). the irq /ft output and the frequency test mode can be used as a measure of the actual frequency of the 32.768khz rtc oscillator. the irq /ft pin is an open-drain output that requires a pullup resistor for proper operation. the ft bit is cleared to 0 on power-up. downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 8 of 20 using the clock alarm the alarm settings and control for the ds1553 resi de within registers 1 ff2hC1ff5h. register 1ff6h contains two alarm-enable bits: alarm enable (ae) and alarm in backup enable (abe). the ae and abe bits must be set as described below for the irq /ft output to be activated for a matched alarm condition. the alarm can be programmed to ac tivate on a specific day of the mo nth or repeat every day, hour, minute, or second. it can also be programmed to go o ff while the ds1553 is in th e battery-backed state of operation to serve as a system wakeup. alarm mask bits am1Cam4 control the alarm mode. table 3 shows the possible settings. configur ations not listed in the table defa ult to the once-per-second mode to notify the user of an incorrect alarm setting. table 3. alarm mask bits am4 am3 am2 am1 alarm rate 1 1 1 1 once per second 1 1 1 0 when seconds match 1 1 0 0 when minutes and seconds match 1 0 0 0 when hours, minutes, and seconds match 0 0 0 0 when date, hours, minutes, and seconds match when the rtc register values match alarm register sett ings, the alarm flag bit (af) is set to 1. if the alarm flag enable (ae) is also set to 1, the alarm condition activates the irq /ft pin. the irq /ft signal is cleared by a read or write to the flags register (address 1ff0h) as shown in figures 2 and 3. when ce is active, the irq /ft signal may be cleared by having the addre ss stable for as short as 15ns and either oe or we active, but it is not guarant eed to be cleared unless t rc is fulfilled. the alarm flag is also cleared by a read or write to the flags register, but the flag does not change states until the end of the read/write cycle and the irq /ft signal has been cleared. downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 9 of 20 figure 2. clearing irq waveforms figure 3. clearing irq waveforms the irq /ft pin can also be activated in the battery-backed mode. the irq /ft goes low if an alarm occurs and both abe and ae are set. the abe and ae bits are cleared durin g the power-up transition, however, an alarm generated during pow er-up sets af. therefore, the af bit can be read after system power-up to determine if an alarm was generated dur ing the power-up sequence. figure 4 illustrates alarm timing during the battery-backup mode and power-up states. figure 4. backup mode alarm waveforms ce = ? ce , downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 10 of 20 using the watchdog timer the watchdog timer can be used to detect an out- of-control processor. the user programs the watchdog timer by setting the desired amount of timeout into the 8-bit watchdog register (address 1ff7h). the five watchdog register bits bmb4Cbmb0 store a binary multiplier and the tw o lower-order bits rb1Crb0 select the resolution, where 00 = 1/ 16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. the watchdog timeout value is then determined by the multiplication of the 5-bit multiplier value with the 2-bit resolution value. (f or example: writing 00001110 in the watchdog register = 3 x 1 second or 3 seconds.) if th e processor does not reset the timer within the specified period, the watchdog flag (wf) is set and a processor interrupt is generated and stays active until either the watchdog flag (wf) is read or the watchdog register (1ff7) is read or written. the most significant bit of the watchdog register is the watchdog steering bit (wds ). when set to 0, the watchdog activates the irq /ft output when the watchdog times out. when wds is set to 1, the watc hdog outputs a negative pulse on the rst output for 40ms to 200ms. the watchdog register (1ff7) and the ft bit are reset to 0 at the end of a watchdog timeout when the wds bit is set to 1. the watchdog timer resets when th e processor performs a read or write of the watchdog register. the timeout period then starts over. writing a value of 00h to the watchdog register disables the watchdog timer. the watchdog function is automatically disa bled upon power-up and th e watchdog register is cleared. if the watchdog functi on is set to output to the irq /ft output and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. power-on default states upon application of power to the device, th e following register b its are set to 0: wds = 0, bmb0Cbmb4 = 0, rb0Crb1 = 0, ae = 0, and abe = 0. downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 11 of 20 absolute maximum ratings voltage range on any pin relative to ground..-0.3v to +6.0v storage temperature range edip .........................-40 ? c to +85 ? c powercap.................-55 ? c to +125 ? c lead temperature (soldering, 10s).........................................................+260c ( note: edip is hand or wave-soldered only.) (note 8) soldering temperature (reflow)..................................................+260c this is a stress rating only and functional ope ration of the device at these or any ot her conditions above those indicated in t he operation sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. operating range range temp range v cc commercial 0c to +70c 3.3v ? 10% or 5v ? 10% recommended dc op erating conditions (t a = over the operating range.) parameter symbol min typ max units notes v cc = 5v 10% v ih 2.2 v cc + 0.3v v 1 logic 1 voltage all inputs v cc = 3.3v 10% v ih 2.0 v cc + 0.3v v 1 v cc = 5v 10% v il -0.3 +0.8 1 logic 0 voltage all inputs v cc = 3.3v 10% v il -0.3 +0.6 1 dc electrical characteristics (v cc = 5.0v ? 10%, t a = over the operating range.) parameter symbol min typ max units notes active supply current i cc 15 50 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 1 3 ma 2, 3 cmos standby current ( ce ? ? v cc - 0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il -1 +1 ? a output leakage current (any output) i ol -1 +1 ? a output logic 1 voltage (i out = -1.0ma) v oh 2.4 v 1 i out = 2.1ma, dq0-7 outputs v ol1 0.4 v 1 output logic 0 voltage i out = 7.0ma, irq /ft and rst outputs v ol2 0.4 v 1, 5 write protection voltage v pf 4.20 4.50 v 1 battery switchover voltage v so v bat v 1, 4 downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 12 of 20 dc electrical characteristics (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol min typ max units notes active supply current i cc 10 30 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 0.7 2 ma 2, 3 cmos standby current ( ce ? ? v cc - 0.2v) i cc2 0.7 2 ma 2, 3 input leakage current (any input) i il -1 +1 ? a output leakage current (any output) i ol -1 +1 ? a output logic 1 voltage (i out = -1.0ma) v oh 2.4 v 1 i out = 2.1ma, dq0C7 outputs v ol1 0.4 v 1 output logic 0 voltage i out = 7.0ma, irq /ft and rst outputs v ol2 0.4 v 1, 5 write protection voltage v pf 2.75 2.97 v 1 battery switchover voltage v so v bat or v pf v 1, 4 figure 5. read cycle timing diagram downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 13 of 20 read cycle, ac ch aracteristics (v cc = 5.0v ? 10%, t a = over the operating range.) 85ns access 100ns access parameter symbol min max min max units read cycle time t rc 85 100 ns address access time t aa 85 100 ns ce to dq low-z t cel 5 5 ns ce access time t cea 85 100 ns ce data off time t cez 30 35 ns oe to dq low-z t oel 5 5 ns oe access time t oea 45 55 ns oe data off time t oez 30 35 ns output hold from address t oh 5 5 ns read cycle, ac ch aracteristics (v cc = 3.3v 10%, t a = over the operating range.) 120ns access 150ns access parameter symbol min max min max units read cycle time t rc 120 150 ns address access time t aa 120 150 ns ce to dq low-z t cel 5 5 ns ce access time t cea 120 150 ns ce data off time t cez 40 50 ns oe to dq low-z t oel 5 5 ns oe access time t oea 100 130 ns oe data off time t oez 35 35 ns output hold from address t oh 5 5 ns downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 14 of 20 write cycle, ac characteristics (v cc = 5.0v 10%, t a = over the operating range.) 85ns access 100ns access parameter symbol min max min max units write cycle time t wc 85 100 ns address access time t as 0 0 ns we pulse width t wew 65 70 ns ce pulse width t cew 70 75 ns data setup time t ds 35 40 ns data hold time t dh 0 0 ns address hold time t ah 5 5 ns we data off time t wez 30 35 ns write recovery time t wr 5 5 ns write cycle, ac characteristics (v cc = 3.3v 10%, t a = over the operating range.) 120ns access 150ns access parameter symbol min max min max units write cycle time t wc 120 150 ns address setup time t as 0 0 ns we pulse width t wew 100 130 ns ce pulse width t cew 110 140 ns data setup time t ds 80 90 ns data hold time t dh 0 0 ns address hold time t ah 0 0 ns we data off time t wez 40 50 ns write recovery time t wr 10 10 ns downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 15 of 20 figure 6. write cycle timing, write-enable controlled figure 7. write cycle timi ng, chip-enable controlled downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 16 of 20 power-up/down characteristics (v cc = 5.0v ? 10%, t a = over the operating range.) parameter symbol min typ max units notes ce or we at v ih , before power-down t pd 0 ? s v cc fall time: v pf(max) to v pf(min) t f 300 ? s v cc fall time: v pf(min) to v so t fb 10 ? s v cc rise time: v pf(min) to v pf(max) t r 0 ? s v pf to rst high t rec 40 200 ms expected data retention time (oscillator on) t dr 10 years 6, 7 figure 8. power-up/down waveform timing 5v device downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 17 of 20 power-up/down characteristics (v cc = 3.3v ? 10%, t a = over the operating range.) parameter symbol min typ max units notes ce or we at v ih , before power-down t pd 0 ? s v cc fall time: v pf(max) to v pf(min) t f 300 ? s v cc rise time: v pf(min) to v pf(max) t r 0 ? s v pf to rst high t rec 40 200 ms expected data retention time (oscillator on) t dr 10 years 6, 7 figure 9. power-up/down w aveform timing 3.3v device capacitance (t a = +25c) parameter symbol min typ max units notes capacitance on all input pins c in 7 pf 1 capacitance on irq /ft, rst , and dq pins c io 10 pf 1 downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 18 of 20 ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0 to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) voltage referenced to ground. 2) typical values are at +25 ? c and nominal supplies. 3) outputs are open. 4) battery switch over occurs at the lowe r of either the battery voltage or v pf . 5) the irq /ft and rst outputs are open drain. 6) data retention time is at +25 ? c. 7) each ds1553 has a built-in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined for dip modules as a cu mulative time in the absence of v cc starting from the time power is first applied by the user. 8) real-time clock modules (dip) can be successfu lly processed through conventional wave-soldering techniques as long as temperatur e exposure to the lithium energy s ource contained within does not exceed +85 ? c. post solder cleaning with water-washing techniques is accep table, provided that ultrasonic vibration is not used. in addition, for the powercap: a. maxim recommends that powercap module bases experience one pass th rough solder reflow oriented with the label side up (live-bug). b. hand soldering and touch-up: do no t touch or apply the soldering ir on to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder. downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 19 of 20 pin configurations package information for the latest packag e outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs stat us only. package drawings may show a di fferent suffix character, but the drawing pertains to the package re gardless of rohs status. package type package code outline no. land pattern no. 28 edip mdp28+2 21-0241 34 pwrcp pc1+2 21-0246 1 i rq / ft 2 3 n.c.n.c. r st v cc w e o e c e dq7dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n.c.n.c. 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 n.c.a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 n.c. x1 gnd v bat x2 34-pin powercap module board (uses ds9034pcx powercap) ds1553 28-pin encapsulated package (700-mil extended) v cc we irq /ft a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rst a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ds1553 top view downloaded from: http:///
ds1553 64kb, nonvolatile, year- 2000-compliant timekeeping ram 20 of 20 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim and the dallas logo are registered trademarks of maxim integrated products, inc. revision history revision date description pages changed 8/10 updated the ordering informatio n table; updated the storage and soldering temperatures and added the lead temperature in the absolute maximum ratings section; changed 70ns access to 85ns access in the read cycle, ac characteristics (5v) table and updated the min/max values for t rc , t aa , t cea , t cez , t oea , and t oez ; changed 70ns access to 85ns access in the write cycle, ac characteristics (5v) table and updated the min/max values for t wc , t wew , t cew , t ds , and t wez ; updated the package information table and removed the package drawings 1, 13, 14, 19 downloaded from: http:///

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